Some metal-insulator-semiconductor (MIS) devices include a gate located in a trench that extends downward from the surface of a semiconductor substrate (e.g., silicon). The current flow in such devices is primarily vertical and, as a result, the cells can be more densely packed. All else being equal, this increases the current carrying capability and reduces the on-resistance of the device. Devices included in the general category of MIS devices include metal-oxide-semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and MOS-gated thyristors.
Trench MOSFETs, for example, can be fabricated with a high transconductance (gm,max) and low specific on resistance (Ron), which are important for optimal linear signal amplification and switching. One of the most important issues for high frequency operation, however, is reduction of the MOSFET internal capacitances. The internal capacitances include the gate-to-drain capacitance (Cgd), which is also called the feedback capacitance (Crss), the input capacitance (Ciss), and the output capacitance (Coss).
FIG. 1 is a cross-sectional view of a conventional n-type trench MOSFET 10. In MOSFET 10, an n-type epitaxial (“N-epi”) layer 13, which is usually grown on an N+ substrate (not shown), is the drain. N-epi layer 13 may be a lightly doped layer, that is, an N− layer. A p-type body region 12 separates N-epi layer 13 from N+ source regions 11. Current flows vertically through a channel (denoted by the dashed lines) along the sidewall of a trench 19. The sidewall and bottom of trench 19 are lined with a thin gate insulator 15 (e.g., silicon dioxide). Trench 19 is filled with a conductive material, such as doped polysilicon, which forms a gate 14. Trench 19, including gate 14 therein, is covered with an insulating layer 16, which may be borophosphosilicate glass (BPSG). Electrical contact to source regions 11 and body region 12 is made with a conductive layer 17, which is typically made of a metal or metal alloy. Gate 14 is contacted in the third dimension, outside of the plane of FIG. 1.
A significant disadvantage of MOSFET 10 is a large overlap region 18 formed between gate 14 and N-epi layer 13, which subjects a portion of thin gate insulator 15 to the drain operating voltage. The large overlap limits the drain voltage rating of MOSFET 10, presents long term reliability issues for thin gate insulator 15, and greatly increases the gate-to-drain capacitance, Cgd, of MOSFET 10. In a trench structure, Cgd is larger than in conventional lateral devices, limiting the switching speed of MOSFET 10 and thus its use in high frequency applications.
One possible method to address this disadvantage is described in the above-referenced application Ser. No. 09/591,179 and is illustrated in FIG. 2. FIG. 2 is a cross-sectional view of a trench MOSFET 20 with an undoped polysilicon plug 22 near the bottom of trench 19. MOSFET 20 is similar to MOSFET 10 of FIG. 1, except for polysilicon plug 22, which is isolated from the bottom of trench 19 by oxide layer 21 and from gate 14 by oxide layer 23. The sandwich of oxide layer 21, polysilicon plug 22, and oxide layer 23 serves to increase the distance between gate 14 and N-epi layer 13, thereby decreasing Cgd.
In some situations, however, it may be preferable to have a material even more insulating than undoped polysilicon in the bottom of trench 19 to minimize Cgd for high frequency applications.
One possible method to address this issue is described in the above-referenced application Ser. No. 09/927,320 and is illustrated in FIG. 3. FIG. 3 is a cross-sectional view of a trench MOSFET 30 with a thick insulating layer 31 near the bottom of trench 19. MOSFET 30 is similar to MOSFET 10 of FIG. 1 and MOSFET 20 of FIG. 2. In MOSFET 30, however, only the sidewall of trench 19 is lined with thin gate insulator 15 (e.g., silicon dioxide). Unlike MOSFET 10 of FIG. 1, a thick insulating layer 31 (e.g., silicon dioxide) lines the bottom of trench 19 of MOSFET 30 of FIG. 3. Thick insulating layer 31 separates gate 14 from N-epi layer 13. This circumvents the problems that occur when only thin gate insulator 15 separates gate 14 from N-epi layer 13 (the drain) as in FIG. 1. Thick insulating layer 31 provides a more effective insulator than is achievable with polysilicon plug 22 as shown in FIG. 2. Thick insulating layer 31 decreases the gate-to-drain capacitance, Cgd, of MOSFET 30 compared to MOSFET 20 of FIG. 2.
The solution of FIG. 3 has a thin gate oxide region 24 between body region 12 and thick insulating layer 31. This is because the bottom interface of body region 12 and the top edge of thick insulating layer 31 are not self-aligned. If body region 12 extends past the top edge of thick insulating layer 31, MOSFET 30 could have a high on-resistance, Ron, and a high threshold voltage. Since such alignment is difficult to control in manufacturing, sufficient process margin can lead to significant gate-to-drain overlap in thin gate oxide regions 24. Thin gate region 24 also exists in MOSFET 20 of FIG. 2, between body region 12 and polysilicon plug 22. Thus, Cgd can still be a problem for high frequency applications. Accordingly, a trench MOSFET with decreased gate-to-drain capacitance, Cgd, and better high frequency performance is desirable.